The present invention according to a first aspect relates to a redundancy system for a functional entity in a digital switch, and a method for providing such a redundancy system.
According to a second aspect the invention relates to a redundancy system for a digital switch with switch inputs and switch outputs and switch equipment therebetween. The switch equipment comprises a switch core and functional entities, a, connection path for data flows between a switch input and a, switch output being able to comprise a number of such functional, entities on both sides of the core. The redundancy system comprises switch planes working in parallel and having mutually essentially identical switch equipment and majority vote functions, distributing means for distributing a data flow coming in from the outside to the equipments of the switch planes, and assembling means for assembling the data flows coming from the switch planes.
According to the second aspect the invention also relates to a method for providing a redundancy structure for a digital switch with switch inputs and switch outputs and switch equipment therebetween, that comprises a switch core and functional entities, a connection path for data flows between a switch input and a switch output being able to comprise a number of such functional entities on both sides of the core.
U.S. Pat. No. 4,706,150 relates to a switching protocol for multiple autonomous switching planes. Supervision is performed of switching in the planes and retrials are provided when connection attempts are unsuccessful. The retrials can consist in a user having established connections through a majority of the planes emitting a retrial request that sets aside the already established connections in the remaining planes. According to an alternative form all users emit retry requests, the planes in accordance with a priority scheme among the users accepting a higher prioritized request and rejecting a lower one.
U.S. Pat. No. 5,278,843 discloses a multiple processor system in which appearance of faults in the microprocessors is decided in accordance with a majority rule and selection is performed on the basis thereof and a predetermined priority order, an output signal being emitted from the microprocessor in which there is no fault and the priority order of which is higher.
In EP 097,781 there is described a method for testing very fast logic systems while using a slow testing device. Different test patterns are used at the testing.
U.S. Pat. No. 4,393,490 relates to digital switch systems with built-in fault identification, there being used i.a. a fault pattern injection.
U.S. Pat. No. 4,535,442, GB 1,393,645, GB 1,439,568 and GB 1,582,456 describe different types of digital switch systems with fault supervision.
Majority vote functions in triplicated redundancy systems have been used during a long time, e.g. in telecommunication equipments.
An example of this appears e.g. from the Swedish patent 466,475.
Use only of majority votes, has in certain cases turned out to be unsufficient when all three planes are not fault free. In particular this is true in case of problems arising at managing the planes in a system due to a fault when a plane or a card is replaced or the system is expanded or reconfigured when changing card types. This can give rise to disturbances on a system level.